In order to improve a data transmission rate of a semiconductor memory device, a synchronous memory device capable of operating in synchronization with a clock signal is being widely used. A synchronous memory device transferring data, for example, on the rising edge of the clock signal is known as a single data rate (SDR) synchronous memory device. Further, a synchronous memory device transferring data on both the rising and falling edges of the clock signal is known as a double data rate (DDR) synchronous memory device. However, the SDR synchronous memory device may not meet speed requirements of a system. Accordingly, the DDR synchronous memory device is being recently used.
The DDR synchronous memory device can implement a band width at least two times larger than the SDR synchronous memory device.
In addition, the swing width of a signal transferred between the semiconductor memory device and a memory controller has been gradually reduced. As the swing width of the signal is reduced, an effect caused by external noise increases, and reflection of signals due to impedance mismatching may become serious at the interface terminal. When impedance mismatching occurs, the signal integrity may deteriorate.
Therefore, an impedance matching circuit called an ODT (On Die Termination) circuit is provided inside a semiconductor memory device. In a known art, at a transmission stage of the ODT circuit, source termination is performed by an output circuit, and at a reception stage thereof, parallel termination is performed by a termination circuit coupled in parallel to a reception circuit coupled to an input pad.
The resistance value of the ODT circuit changes depending on a PVT (Process, Voltage, and Temperature) condition. Therefore, the semiconductor integrated circuit includes an impedance calibration circuit configured to perform a ZQ calibration operation by using an external resistor, in order to control the changing resistance value of the ODT circuit.
FIG. 1 is a diagram illustrating the configuration of a known impedance calibration circuit.
Referring to FIG. 1, the known impedance calibration circuit includes a pad 11 coupled to an external resistor R, comparators 12 and 16, counters 13 and 17, pull-up units 14 and 15, and a pull-down unit 18.
The operation of the impedance calibration circuit configured in such a manner is performed as follows.
First, the comparator 12 compares a pad voltage ZQ with a reference voltage VREF and drives the counter 13 which counts a pull-up code PCODE<1:N> to equalize resistance values of the pull-up units 14 and 15 to that of the external resistor R. When the resistance values of the pull-up units 14 and 15 are equalized to that of the external resistor R by the pull-up code PCODE<1:N> counted by the counter 13, the counter 13 is stopped.
Next, the comparator 16 compares a voltage of a node nd10 with the reference voltage VREF and drives the counter 17 which counts a pull-down code NCODE<1:N> to equalize the resistance value of the pull-down unit 18 to that of the pull-up unit 15. When the resistance value of the pull-down unit 18 is equalized to that of the pull-up unit 15 by the pull-down code NCODE<1:N> counted by the counter 17, the counter 17 stops counting.
As described above, the impedance calibration circuit equalizes the resistance values of the pull-up units 14 and 15 to that of the external resistor R, and then equalizes the resistance value of the pull-down unit 18 to that of the pull-up unit 15. That is, the impedance calibration circuit equalizes the resistance values of the pull-up units 14 and 15 and the pull-down unit 18 to that of the external resistor R having a constant resistance value depending on changes in the PVT condition.
In addition, when a semiconductor integrated circuit including the impedance calibration circuit is packaged, the pad 11 of the impedance calibration circuit is bonded and coupled to a ZQ pin of a package (not illustrated). However, since the ZQ pin cannot be tested after the packaging, it may be difficult to check whether the pad 11 of the impedance calibration circuit is coupled or not.